Design of an Area efficient BISR scheme For Multiple Memories

Abstract

The Proposed Built-in self-repair (BISR) scheme for multiple embedded memories to find optimum point of the performance of BISR for multiple embedded memories. All memories are concurrently tested by the small dedicated built-in self-test to figure out the faulty memories, the number of faults, and irreparability. After all memories are tested, only faulty memories are serially tested and repaired by the shared built-in redundancy analysis according to the sizes of memories in descending order. Thus, the fast test and repair are performed with low area overhead. To accomplish an optimal repair rate and a fast analysis speed, an exhaustive search for all combinations of spare rows and columns is proposed based on the optimized fault collection. In proposed BISR includes BIST and BIRA, The BIST is design by using of March X algorithm.

By using this algorithm the delay and area is reduced. This proposed design is programmed using Verilog - HDL using Xilinx ISE 14.7. The FPGA implementation is done on Spartan3E.

Index Terms— Built-in redundancy analysis (BIRA), built-in self-repair (BISR), built-in self-test (BIST), March X algorithm.